The present invention relates to a multi-processor system having a shared memory unit and more particularly to a multi-processor type storage control apparatus.
In recent storage systems, a system of the type having multi-processor architecture has been employed principally with the aim of obtaining higher performance.
For example, in a prior art shown in “HITAC H8538-C3 type disc control apparatus”, p5, 1985, the apparatus has storage directors each of which controls data transfer between a central processing unit (CPU) and a storage unit, and a cache memory that temporally stores data of the storage units. The two or more storage directors are connected to the cache memory and each of the storage directors has an access path to the cache memory. Such an arrangement is called “star connection”. There are processors running micro programs that control data transmission and related hardware in the storage director. The apparatus also has a shared memory which stores information, such as cache and disc management data, with-which the processors work consistently. The storage directors and the shared memory are connected in a similar manner to the cache memory through different access paths.
On the other hand, in another prior art shown in “HITAC A6591 type disc control apparatus”, p4, 1997, the control apparatus has a plurality of processors on the host side, a plurality of processors on the storage unit side, a cache memory unit and a shared memory unit. Each of the processors is coupled to the shared memory unit through a control bus and each of the processors is coupled to the cache memory unit through a data bus.
In the above prior arts, the shared memory unit has a dual structure of shared memory sections with the aim of securing the reliability, so that even when one of the shared memory sections is blocked, normal operation of the system can be ensured. In the conventional system, for the purpose of maintaining the dual state of the shared memory unit, a method is employed in which when write access to the shared memory unit occurs, circuits of both the shared memory sections receive the access and at the same time, update a designated address.
On the other hand, in the former prior art, such control as above is not carried out and when there occurs updating, addresses on both the shared memory sections are updated sequentially in accordance with a program operated by the processor.